Global shutter image sensor

ABSTRACT

In one example, a method comprises: within an integration period: enabling a photodiode of a pixel cell to accumulate charge responsive to incident light, and transferring the charge from the photodiode to a charge storage device of the pixel cell. The method further comprises: performing, using a sampling capacitor, a sample-and-hold operation to convert the charge stored in the charge storage device into a voltage; and generating a digital output based on the voltage to represent an intensity of the incident light received by the photodiode.

RELATED APPLICATION

This patent application is a continuation of U.S. Non-Provisional patentapplication Ser. No. 16/369,763, filed Mar. 29, 2019, entitled “GLOBALSHUTTER IMAGE SENSOR”, which claims priority to U.S. Provisional PatentApplication Ser. No. 62/652,220, filed Apr. 3, 2018, entitled “GLOBALSHUTTER IMAGE SENSOR,” which is assigned to the assignee hereof and isincorporated herein by reference in its entirety for all purposes.

BACKGROUND

The disclosure relates generally to image sensors, and more specificallyto pixel cell structure including interfacing circuits to determinelight intensity for image generation.

A typical image sensor includes an array of photodiodes to senseincident light by converting photons into charge (e.g., electrons orholes). To reduce image distortion, a global shutter operation can beperformed in which each photodiode of the array of photodiodes sensesthe incident light simultaneously to generate charge. The chargegenerated by the array of photodiodes can then be quantized by ananalog-to-digital converter (ADC) into digital values to generate theimage.

SUMMARY

The present disclosure relates to image sensors. More specifically, andwithout limitation, this disclosure relates to a pixel cell. Thisdisclosure also relates to operating the circuitries of pixel cells togenerate a digital representation of the intensity of incident light.

In one example, a pixel cell is provided. The pixel cell includes afirst semiconductor die, the first semiconductor die including aphotodiode and a charge sensing device. The pixel cell further includesa sampling capacitor, and a second semiconductor die forming a stackwith the first semiconductor die, the second semiconductor die includingan interface circuit coupled with the photodiode, the charge sensingdevice, and the sampling capacitor. The interface circuit is configuredto: enable the photodiode to accumulate charge responsive to incidentlight within a integration period; transfer the charge from thephotodiode to the charge sensing device; perform, using the samplingcapacitor, a sample-and-hold operation to convert the charge in thecharge sensing device into a voltage; and generate a digital outputbased on the voltage to represent an intensity of the incident lightreceived by the photodiode.

In some aspects, the pixel cell further includes a sampling switchcoupled between the charge sensing device and the sampling capacitor.The interface circuit is configured to, as part of the sample-and-holdoperation: enable the sampling switch to cause the sampling capacitor tosample the charge accumulated in the charge sensing device to developthe voltage; and disable the sampling switch to cause the samplingcapacitor to hold the voltage.

In some aspects, the voltage is a first voltage. The charge sensingdevice is configured to output a second voltage based on the storedcharge. The pixel cell further includes a voltage buffer coupled betweenthe charge sensing device and the sampling capacitor and configured tobuffer the second voltage to output the first voltage to the samplingcapacitor. The sampling capacitor is operated to sample the firstvoltage received from the voltage buffer when the sampling switch isenabled, and to hold the first voltage after the sampling switch isdisabled.

In some aspects, the sampling switch and the voltage buffer are includedin the first semiconductor die.

In some aspects, the sampling capacitor includes at least one of: ametal capacitor or a semiconductor capacitor sandwiched between thefirst semiconductor die and the second semiconductor die in the stack,or a metal capacitor or a semiconductor capacitor formed in the secondsemiconductor die.

In some aspects, the interface circuit further comprises a resettablecomparator. The pixel cell further comprises an AC capacitor coupledbetween the sampling capacitor and the comparator. The interface circuitis configured to, when the sampling switch is enabled: control thecomparator to enter a reset state; operate the AC capacitor to: obtain afirst sample of a reset voltage of the charge sensing device caused by aprior reset operation of the charge sensing device; obtain a secondsample of an offset of the comparator when the comparator is in thereset state; store a third voltage across the AC capacitor based on thefirst sample of the reset voltage and the second sample of the offset;and output a fourth voltage to the comparator based on the first voltageand the third voltage. The digital output is generated based on thefourth voltage.

In some aspects, the pixel cell further comprises a transfer switchcoupled between the photodiode and the charge sensing device. Theinterface circuit is configured to: control the comparator to exit thereset state to hold the third voltage across the AC capacitor; enablethe transfer switch to transfer the charge from the photodiode to thecharge sensing device, wherein the transfer of the charge develops thefirst voltage at the sampling capacitor; and disable the transfer switchto stop the transfer of the charge, wherein the disabling of thetransfer switch causes the sampling capacitor to hold the first voltageand the AC capacitor to hold the fourth voltage for the generation ofthe digital output.

In some aspects, an output of the comparator of the pixel cell iscoupled with a memory. The memory is coupled with a counter configuredto update a count value periodically based on a clock. The comparator isconfigured to, after the transfer switch is disabled, compare the fourthvoltage against a ramping threshold to output a decision. The memory isconfigured to store the count value from the counter based on thedecision. The stored count value represents the digital output.

In some aspects, the pixel cell further comprises a selection switchcoupled between the output of the comparator and the memory. Theinterface circuit is configured to: enable the selection switch totransmit the decision to the memory when the pixel cell is selected tostore the digital output in the memory; and disable the selection switchto block the decision from the memory when the pixel cell is notselected to store the digital output in the memory.

In some aspects, the memory and the counter are included in the secondsemiconductor die.

In some aspects, the pixel cell further comprises a shutter switchcoupled between the photodiode and a charge sink. The interface circuitis configured to: disable the shutter switch to start the integrationperiod and to enable the photodiode to accumulate the charge, and enablethe shutter switch to end the integration period and to prevent thephotodiode from accumulating the charge.

In some aspects, the charge sensing device comprises at least one of: afloating drain node, or a pinned storage node.

In some examples, an image sensor is provided. The image sensorcomprises a first semiconductor die, the first semiconductor dieincluding an array of light sensing circuits, each light sensing circuitof the array of light sensing circuits comprising a photodiode and acharge sensing device. The image sensor further comprises an array ofsampling capacitors, each sampling capacitor of the array of samplingcapacitors corresponding to a light sensing circuit of the array oflight sensing circuits. The image sensor further comprises a secondsemiconductor die forming a stack with the first semiconductor die, thesecond semiconductor die including an array of interface circuits, eachinterface circuit of the array of interface circuits, each light sensingcircuit of the array of light sensing circuits, and each samplingcapacitor of the array of sampling capacitors forming a pixel cell. Eachinterface circuit of the each pixel cell is configured to: enable thephotodiode of the corresponding light sensing circuit to accumulatecharge responsive to incident light within a global integration period;transfer the charge from the photodiode to the charge sensing device ofthe corresponding light sensing circuit; perform, using thecorresponding sampling capacitor, a sample-and-hold operation on thecharge stored in the charge sensing device to obtain a voltage; andgenerate a digital output based on the voltage to represent an intensityof the incident light received by the corresponding pixel cell.

In some aspects, in the each pixel cell: the light sensing circuitfurther includes a sampling switch coupled between the charge sensingdevice and the sampling capacitor. The interface circuit is configuredto, as part of the sample-and-hold operation: enable the sampling switchto cause the sampling capacitor to sample the charge stored in thecharge sensing device to develop the voltage; and disable the samplingswitch to cause the sampling capacitor to hold the voltage.

In some aspects, in the each pixel cell: the voltage is a first voltage.The charge sensing device is configured to output a second voltage basedon the stored charge. The light sensing circuit further includes avoltage buffer coupled between the charge sensing device and thesampling capacitor and configured to buffer the second voltage to outputthe first voltage to the sampling capacitor. The sampling capacitor isoperated to sample the first voltage received from the voltage bufferwhen the sampling switch is enabled, and to hold the first voltage afterthe sampling switch is disabled.

In some aspects, in the each pixel cell: the each interface circuitfurther comprises a resettable comparator. The each light sensingcircuit further comprises an AC capacitor coupled between the samplingcapacitor and the comparator. The each interface circuit is configuredto, when the sampling switch is enabled: control the comparator to entera reset state; operate the AC capacitor to: obtain a first sample of areset voltage of the charge sensing device caused by a prior resetoperation of the charge sensing device; obtain a second sample of anoffset of the comparator when the comparator is in the reset state;store a third voltage across the AC capacitor based on the first sampleof the reset voltage and the second sample of the offset; and output afourth voltage to the comparator based on the first voltage and thethird voltage. The digital output is generated based on the fourthvoltage.

In some aspects, the each light sensing circuit further comprises atransfer switch coupled between the photodiode and the charge sensingdevice. The each interface circuit is configured to: control thecomparator to exit the reset state to hold the third voltage across theAC capacitor; enable the transfer switch to transfer the charge from thephotodiode to the charge sensing device, wherein the transfer of thecharge develops the first voltage at the sampling capacitor; and disablethe transfer switch to stop the transfer of the charge, wherein thedisabling of the transfer switch causes the sampling capacitor to holdthe first voltage and the AC capacitor to hold the fourth voltage forthe generation of the digital output.

In some aspects, the image sensor further includes a controller, acounter, and a bank of memory buffers. Each memory buffer of the bank ofmemory buffers is coupled with the counter. The counter is configured toupdate a count value periodically based on a clock. An output of thecomparator of the each interface circuit is coupled to the each memorybuffer via a selection switch controlled by the controller. Thecomparator is configured to, after the transfer switch is disabled,compare the fourth voltage against a ramping threshold to generate adecision. The controller is configured to, at different times, enablethe selection switches of subsets of the pixel cells to transmit thedecisions of the comparators of the selected subsets of the pixel cellsto the bank of memory buffers. The bank of memory buffers is configuredto store the count values from the counter based on the decisions of theselected subsets of the pixel cells at the different times. The storedcount values represent the digital outputs of the pixel cells.

In some example, a method is provided. The method comprises: enabling,by an interface circuit, a photodiode of a light sensing circuit toaccumulate charge responsive to incident light within a integrationperiod, wherein the light sensing circuit and the interface circuit arein, respectively, a first semiconductor die and a second semiconductordie forming a stack; transferring, by the interface circuit, the chargefrom the photodiode to a charge sensing device of the light sensingcircuit; performing, by the interface circuit and using a samplingcapacitor, a sample-and-hold operation to convert the charge stored inthe charge sensing device into a voltage; and generating, by theinterface circuit, a digital output based on the voltage to represent anintensity of the incident light received by the photodiode.

In some aspects, the method further comprises: comparing the voltagewith a ramping threshold to output a decision; controlling a memory tostore a count value from a counter based on the decision; and providingthe count value as the digital output. The memory and the counter is inthe second semiconductor die.

BRIEF DESCRIPTION OF THE DRAWINGS

Illustrative embodiments are described with reference to the followingfigures.

FIG. 1A and FIG. 1B are diagrams of an embodiment of a near-eye display.

FIG. 2 is an embodiment of a cross section of the near-eye display.

FIG. 3 illustrates an isometric view of an embodiment of a waveguidedisplay with a single source assembly.

FIG. 4 illustrates a cross section of an embodiment of the waveguidedisplay.

FIG. 5 is a block diagram of an embodiment of a system including thenear-eye display.

FIG. 6A, FIG. 6B, and FIG. 6C illustrate examples of a pixel cell andtheir operations.

FIG. 7A, FIG. 7B, FIG. 7C, FIG. 7D, and FIG. 7E illustrate examples of apixel cell and its operations.

FIG. 8A, FIG. 8B, FIG. 8C, FIG. 8D, and FIG. 8E illustrate an example ofan image sensor and their operations.

FIG. 9 illustrates a flowchart of an example process for measuring lightintensity.

The figures depict embodiments of the present disclosure for purposes ofillustration only. One skilled in the art will readily recognize fromthe following description that alternative embodiments of the structuresand methods illustrated may be employed without departing from theprinciples, or benefits touted, of this disclosure.

In the appended figures, similar components and/or features may have thesame reference label. Further, various components of the same type maybe distinguished by following the reference label by a dash and a secondlabel that distinguishes among the similar components. If only the firstreference label is used in the specification, the description isapplicable to any one of the similar components having the same firstreference label irrespective of the second reference label.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, specificdetails are set forth in order to provide a thorough understanding ofcertain inventive embodiments. However, it will be apparent that variousembodiments may be practiced without these specific details. The figuresand description are not intended to be restrictive.

A typical image sensor includes an array of pixel cells. Each pixel cellincludes a photodiode to sense incident light by converting photons intocharge (e.g., electrons or holes). The charge generated by photodiodesof the array of pixel cells can then be quantized by ananalog-to-digital converter (ADC) into digital values. The ADC canquantize the charge by, for example, using a comparator to compare avoltage representing the charge with one or more quantization levels,and a digital value can be generated based on the comparison result. Thedigital values can then be stored in a memory to generate the image.

Due to power and chip area limitation, typically the ADC and the memoryare shared by at least some of the pixel cells, instead of providing adedicated ADC and a memory to each pixel cell. A rolling shutteroperation can be performed to accommodate the sharing of the ADC and thememory among the pixel cells. For example, the array of pixel cells canbe divided into multiple groups (e.g., rows or columns of pixel cells),with the pixels of each group sharing an ADC and the memory. Toaccommodate the sharing of the ADC and the memory, a rolling shutteroperation can be performed in which each pixel cell within the group cantake a turn to be exposed to incident light to generate the charge,followed by accessing the ADC to perform the quantization of the chargeinto a digital value, and storing the digital value into the memory. Asthe rolling shutter operation exposes different pixel cells to incidentlight at different times, an image generated from the rolling shutteroperation can experience distortion, especially for images of a movingobject and/or images captured when the image sensor is moving. Thepotential distortion introduced by rolling shutter operation makes itunsuitable for augmented reality/mixed reality/virtual reality(AR/MR/VR) applications, wearable applications, etc., in which the imagesensor can be part of a headset and can be in motion when capturingimages.

To reduce image distortion, a global shutter operation can be performedin which each pixel cell of the array of pixel cells is exposed toincident light to generate charge simultaneously within a global shutterperiod (or a global integration period). Each pixel cell can include acharge sensing device to temporarily store the charge generated by thephotodiode. When the pixel cell is granted access to the ADC and to thememory, the pixel cell can provide the charge from the charge sensingdevice to the ADC to perform the quantization to generate the digitalvalue, and then store the digital value in the memory.

There are various techniques to implement a charge sensing device in apixel cell, such as implementing the charge sensing device as a floatingdrain node, a pinned storage node (of a pinned diode), etc. But a chargesensing device implemented using these techniques is susceptible tonoise charge, which can degrade the correlation between the chargestored in the charge sensing device and the incident light intensity andreduce the sensitivity of the pixel cell. For example, a floating drainnode configured as a charge sensing device can be susceptible to darkcurrent, which can be leakage currents generated at the p-n junction ofa semiconductor device due to crystallographic defects. The dark currentcan flow into the charge sensing device and add to the charge generatedby the photodiode. As another example, a pinned storage node cangenerate charge when photons of the incident light penetrate into thesemiconductor substrate of the pixel cell and reach the pinned storagenode. The charge generated by the charge sensing device can add to thecharge generated by the photodiode. In both cases, the charge stored inthe charge sensing device is different from the charge generated by thephotodiode during the global shutter period, and the quantization resultof the charge in the charge sensing device may not provide an accuraterepresentation of the incident light intensity.

There are other noise sources that can further degrade the accuraterepresentation of the incident light intensity. For example, during thereset of the charge sensing device between measurements, thermal noise(as well as other noises, such as 1/f noise, etc.) can be injected intothe charge sensing device as reset noise, which adds charge notreflecting the incident light intensity to the floating node. Moreover,as discussed above, the quantization process typically includes using acomparator to compare a voltage representing the charge with one or morequantization levels, and a digital value can be generated based on theresults of the comparisons. The comparator offset can also lead toerrors in the comparison with the quantization levels, which canintroduce errors in the digital value.

This disclosure relates to a pixel cell that can improve a globalshutter operation. In one example, a pixel cell can include a firstsemiconductor die, a sampling capacitor, and a second semiconductor die.The first semiconductor die includes a light receiving surface, aphotodiode to receive incident light via the light receiving surface,and a charge sensing device to accumulate charge generated by thephotodiode. The second semiconductor die forms a stack with the firstsemiconductor die and includes an interface circuit coupled with thesampling capacitor, the photodiode, and the charge sensing device. Thesampling capacitor may include a metal capacitor sandwiched between thefirst and second semiconductor dies within the stack, or may include adevice capacitor formed in the second semiconductor die. The chargesensing device may include a floating drain node, a pinned storage node,etc.

To perform sensing of incident light, the interface circuit can exposethe photodiode to the incident light within an integration period tocause the photodiode to generate charge. The interface circuit canperform, using the sampling capacitor, a sample-and-hold operation onthe charge accumulated in the storage device within the integrationperiod to obtain a voltage. More specifically, the pixel cell caninclude a sampling switch coupled between the charge sensing device andthe sampling capacitor to support the sample-and-hold operation. Theinterface circuit can enable the sampling switch to cause the samplingcapacitor to sample the charge accumulated in the storage device todevelop the voltage, and then disable the sampling switch to cause thesampling capacitor to hold the voltage. The voltage held at the samplingcapacitor, after the sampling switch is disabled, can be quantized togenerate the digital output.

The interface circuit of the pixel cell may include a comparator toperform the quantization. The comparator can be coupled with a memoryand a counter, both of which can be external to the pixel cell. Thecounter can update a count value periodically based on a clock. Thecomparator can compare the voltage held at the sampling capacitoragainst a ramping threshold to generate a decision. Based on thedecision, the memory can store the count value from the counter. Thecount value stored in the memory can be the digital output.

In some examples, to further improve the accuracy of sensing of theincident light, an AC capacitor can be provided between the samplingcapacitor and the comparator to store a second voltage representing thereset noise introduced to the charge sensing device and the offset ofthe comparator. The AC capacitor can also include a metal capacitorsandwiched between the first and second semiconductor dies within thestack. The AC capacitor can combine the second voltage with the voltageheld at the sampling capacitor (“a first voltage”) to output a thirdvoltage to the comparator, with the reset noise component removed fromthe third voltage as a result of the combination. The comparator cancompare the third voltage with the thresholds to perform thequantization operation, in which the comparator offset component in thethird voltage can compensate for the actual offset of the comparator.

The disclosed techniques can improve light sensing in numerous ways.First, the sampling capacitor can provide an additional charge sensingdevice to store the charge generated by the photodiode. The samplingcapacitor can also be less susceptible to noise charge. For example, thesampling capacitor can be a metal capacitor which is less susceptible todark current due to crystallographic defects and which does not generatecharge when receiving photons. Combined with the techniques ofpre-storing the reset noise and the comparator offset in an AC capacitorto reduce the effect of the reset noise and comparator offset on thequantization operation as described above, the accuracy of the lightsensing operation, and the fidelity of the image generation operation,can be substantially improved.

The disclosed techniques can also reduce the footprint of the pixelcells, which allows packing a large number of pixel cells in an imagesensor to improve resolution while minimizing the footprint of the imagesensor. For example, by stacking the photodiode with the processingcircuit to form a pixel cell, and by putting the memory external to thepixel cell, the footprint of the pixel cell can be reduced. Moreover, byforming the sampling capacitor and the AC capacitor between thesemiconductor dies, these capacitors do not cover the light receivingsurface, which can maximize the available pixel cell area for the lightreceiving surface and allows the footprint of the pixel cell to befurther reduced. With the disclosed techniques, a high resolution imagesensor with a small footprint can be achieved, which is especiallyuseful for applications on a wearable device (e.g., a headset) whereavailable space is very limited.

The disclosed techniques can also improve reliability and speed of imagegeneration. For example, as the memory is positioned outside the pixelcell and does not affect the footprint of the pixel cell, redundantmemory devices can be provided to store the digital outputs from eachpixel cell to reduce the likelihood of losing the digital outputs (andthe pixel values) due to defective memory. But since the memorycomprises mostly digital circuits and typically has a very smallfootprint, adding redundant memory (to be shared by the pixel cells)typically does not significantly increase the footprint of the imagesensor. Moreover, compared with an implementation where the pixel celltransmits an analog voltage (e.g., a voltage at the charge sensingdevice) to an external ADC to perform the quantization operation, thedisclosed techniques allow a part of the quantization (the comparatorcomparison) operation to be performed within the pixel cell, and only adigital output (the decision of the comparator) is transmitted from thepixel cell to the external memory. Compared with an analog voltage, thedigital output can be transmitted with high fidelity (to distinguishbetween zeroes and ones) and at high speed. All these can improve thereliability and speed of image generation based on the light sensingoperations by the pixel cells.

The disclosed techniques may include or be implemented in conjunctionwith an artificial reality system. Artificial reality is a form ofreality that has been adjusted in some manner before presentation to auser, which may include, e.g., a virtual reality (VR), an augmentedreality (AR), a mixed reality (MR), a hybrid reality, or somecombination and/or derivatives thereof. Artificial reality content mayinclude completely generated content or generated content combined withcaptured (e.g., real-world) content. The artificial reality content mayinclude video, audio, haptic feedback, or some combination thereof, anyof which may be presented in a single channel or in multiple channels(such as stereo video that produces a three-dimensional effect to theviewer). Additionally, in some embodiments, artificial reality may alsobe associated with applications, products, accessories, services, orsome combination thereof, that are used to, e.g., create content in anartificial reality and/or are otherwise used in (e.g., performactivities in) an artificial reality. The artificial reality system thatprovides the artificial reality content may be implemented on variousplatforms, including a head-mounted display (HMD) connected to a hostcomputer system, a standalone HMD, a mobile device or computing system,or any other hardware platform capable of providing artificial realitycontent to one or more viewers.

FIG. 1A is a diagram of an embodiment of a near-eye display 100.Near-eye display 100 presents media to a user. Examples of mediapresented by near-eye display 100 include one or more images, video,and/or audio. In some embodiments, audio is presented via an externaldevice (e.g., speakers and/or headphones) that receives audioinformation from the near-eye display 100, a console, or both, andpresents audio data based on the audio information. Near-eye display 100is generally configured to operate as a virtual reality (VR) display. Insome embodiments, near-eye display 100 is modified to operate as anaugmented reality (AR) display and/or a mixed reality (MR) display.

Near-eye display 100 includes a frame 105 and a display 110. Frame 105is coupled to one or more optical elements. Display 110 is configuredfor the user to see content presented by near-eye display 100. In someembodiments, display 110 comprises a waveguide display assembly fordirecting light from one or more images to an eye of the user.

Near-eye display 100 further includes image sensors 120 a, 120 b, 120 c,and 120 d. Each of image sensors 120 a, 120 b, 120 c, and 120 d mayinclude a pixel array configured to generate image data representingdifferent fields of views along different directions. For example,sensors 120 a and 120 b may be configured to provide image datarepresenting two fields of view towards a direction A along the Z axis,whereas sensor 120 c may be configured to provide image datarepresenting a field of view towards a direction B along the X axis, andsensor 120 d may be configured to provide image data representing afield of view towards a direction C along the X axis.

In some embodiments, sensors 120 a-120 d can be configured as inputdevices to control or influence the display content of the near-eyedisplay 100, to provide an interactive VR/AR/MR experience to a user whowears near-eye display 100. For example, sensors 120 a-120 d cangenerate physical image data of a physical environment in which the useris located. The physical image data can be provided to a locationtracking system to track a location and/or a path of movement of theuser in the physical environment. A system can then update the imagedata provided to display 110 based on, for example, the location andorientation of the user, to provide the interactive experience. In someembodiments, the location tracking system may operate a SLAM algorithmto track a set of objects in the physical environment and within a viewof field of the user as the user moves within the physical environment.The location tracking system can construct and update a map of thephysical environment based on the set of objects, and track the locationof the user within the map. By providing image data corresponding tomultiple fields of views, sensors 120 a-120 d can provide the locationtracking system a more holistic view of the physical environment, whichcan lead to more objects to be included in the construction and updatingof the map. With such an arrangement, the accuracy and robustness oftracking a location of the user within the physical environment can beimproved.

In some embodiments, near-eye display 100 may further include one ormore active illuminators 130 to project light into the physicalenvironment. The light projected can be associated with differentfrequency spectrums (e.g., visible light, infra-red light, ultra-violetlight, etc.), and can serve various purposes. For example, illuminator130 may project light in a dark environment (or in an environment withlow intensity of infra-red light, ultra-violet light, etc.) to assistsensors 120 a-120 d in capturing images of different objects within thedark environment to, for example, enable location tracking of the user.Illuminator 130 may project certain markers onto the objects within theenvironment, to assist the location tracking system in identifying theobjects for map construction/updating.

In some embodiments, illuminator 130 may also enable stereoscopicimaging. For example, one or more of sensors 120 a or 120 b can includeboth a first pixel array for visible light sensing and a second pixelarray for infra-red (IR) light sensing. The first pixel array can beoverlaid with a color filter (e.g., a Bayer filter), with each pixel ofthe first pixel array being configured to measure intensity of lightassociated with a particular color (e.g., one of red, green or bluecolors). The second pixel array (for IR light sensing) can also beoverlaid with a filter that allows only IR light through, with eachpixel of the second pixel array being configured to measure intensity ofIR lights. The pixel arrays can generate an RGB image and an IR image ofan object, with each pixel of the IR image being mapped to each pixel ofthe RGB image. Illuminator 130 may project a set of IR markers on theobject, the images of which can be captured by the IR pixel array. Basedon a distribution of the IR markers of the object as shown in the image,the system can estimate a distance of different parts of the object fromthe IR pixel array, and generate a stereoscopic image of the objectbased on the distances. Based on the stereoscopic image of the object,the system can determine, for example, a relative position of the objectwith respect to the user, and can update the image data provided todisplay 100 based on the relative position information to provide theinteractive experience.

As discussed above, near-eye display 100 may be operated in environmentsassociated with a very wide range of light intensities. For example,near-eye display 100 may be operated in an indoor environment or in anoutdoor environment, and/or at different times of the day. Near-eyedisplay 100 may also operate with or without active illuminator 130being turned on. As a result, image sensors 120 a-120 d may need to havea wide dynamic range to be able to operate properly (e.g., to generatean output that correlates with the intensity of incident light) across avery wide range of light intensities associated with different operatingenvironments for near-eye display 100.

FIG. 1B is a diagram of another embodiment of near-eye display 100. FIG.1B illustrates a side of near-eye display 100 that faces the eyeball(s)135 of the user who wears near-eye display 100. As shown in FIG. 1B,near-eye display 100 may further include a plurality of illuminators 140a, 140 b, 140 c, 140 d, 140 e, and 140 f. Near-eye display 100 furtherincludes a plurality of image sensors 150 a and 150 b. Illuminators 140a, 140 b, and 140 c may emit lights of certain frequency range (e.g.,NIR) towards direction D (which is opposite to direction A of FIG. 1A).The emitted light may be associated with a certain pattern, and can bereflected by the left eyeball of the user. Sensor 150 a may include apixel array to receive the reflected light and generate an image of thereflected pattern. Similarly, illuminators 140 d, 140 e, and 140 f mayemit NIR lights carrying the pattern. The NIR lights can be reflected bythe right eyeball of the user, and may be received by sensor 150 b.Sensor 150 b may also include a pixel array to generate an image of thereflected pattern. Based on the images of the reflected pattern fromsensors 150 a and 150 b, the system can determine a gaze point of theuser, and update the image data provided to display 100 based on thedetermined gaze point to provide an interactive experience to the user.

As discussed above, to avoid damaging the eyeballs of the user,illuminators 140 a, 140 b, 140 c, 140 d, 140 e, and 140 f are typicallyconfigured to output lights of very low intensities. In a case whereimage sensors 150 a and 150 b comprise the same sensor devices as imagesensors 120 a-120 d of FIG. 1A, the image sensors 120 a-120 d may needto be able to generate an output that correlates with the intensity ofincident light when the intensity of the incident light is very low,which may further increase the dynamic range requirement of the imagesensors.

Moreover, the image sensors 120 a-120 d may need to be able to generatean output at a high speed to track the movements of the eyeballs. Forexample, a user's eyeball can perform a very rapid movement (e.g., asaccade movement) in which there can be a quick jump from one eyeballposition to another. To track the rapid movement of the user's eyeball,image sensors 120 a-120 d need to generate images of the eyeball at highspeed. For example, the rate at which the image sensors generate animage frame (the frame rate) needs to at least match the speed ofmovement of the eyeball. The high frame rate requires short totalexposure time for all of the pixel cells involved in generating theimage frame, as well as high speed for converting the sensor outputsinto digital values for image generation. Moreover, as discussed above,the image sensors also need to be able to operate at an environment withlow light intensity.

FIG. 2 is an embodiment of a cross section 200 of near-eye display 100illustrated in FIG. 1. Display 110 includes at least one waveguidedisplay assembly 210. An exit pupil 230 is a location where a singleeyeball 220 of the user is positioned in an eyebox region when the userwears the near-eye display 100. For purposes of illustration, FIG. 2shows the cross section 200 associated eyeball 220 and a singlewaveguide display assembly 210, but a second waveguide display is usedfor a second eye of a user.

Waveguide display assembly 210 is configured to direct image light to aneyebox located at exit pupil 230 and to eyeball 220. Waveguide displayassembly 210 may be composed of one or more materials (e.g., plastic,glass, etc.) with one or more refractive indices. In some embodiments,near-eye display 100 includes one or more optical elements betweenwaveguide display assembly 210 and eyeball 220.

In some embodiments, waveguide display assembly 210 includes a stack ofone or more waveguide displays including, but not restricted to, astacked waveguide display, a varifocal waveguide display, etc. Thestacked waveguide display is a polychromatic display (e.g., ared-green-blue (RGB) display) created by stacking waveguide displayswhose respective monochromatic sources are of different colors. Thestacked waveguide display is also a polychromatic display that can beprojected on multiple planes (e.g., multi-planar colored display). Insome configurations, the stacked waveguide display is a monochromaticdisplay that can be projected on multiple planes (e.g., multi-planarmonochromatic display). The varifocal waveguide display is a displaythat can adjust a focal position of image light emitted from thewaveguide display. In alternate embodiments, waveguide display assembly210 may include the stacked waveguide display and the varifocalwaveguide display.

FIG. 3 illustrates an isometric view of an embodiment of a waveguidedisplay 300. In some embodiments, waveguide display 300 is a component(e.g., waveguide display assembly 210) of near-eye display 100. In someembodiments, waveguide display 300 is part of some other near-eyedisplay or other system that directs image light to a particularlocation.

Waveguide display 300 includes a source assembly 310, an outputwaveguide 320, and a controller 330. For purposes of illustration, FIG.3 shows the waveguide display 300 associated with a single eyeball 220,but in some embodiments, another waveguide display separate, orpartially separate, from the waveguide display 300 provides image lightto another eye of the user.

Source assembly 310 generates image light 355. Source assembly 310generates and outputs image light 355 to a coupling element 350 locatedon a first side 370-1 of output waveguide 320. Output waveguide 320 isan optical waveguide that outputs expanded image light 340 to an eyeball220 of a user. Output waveguide 320 receives image light 355 at one ormore coupling elements 350 located on the first side 370-1 and guidesreceived input image light 355 to a directing element 360. In someembodiments, coupling element 350 couples the image light 355 fromsource assembly 310 into output waveguide 320. Coupling element 350 maybe, e.g., a diffraction grating, a holographic grating, one or morecascaded reflectors, one or more prismatic surface elements, and/or anarray of holographic reflectors.

Directing element 360 redirects the received input image light 355 todecoupling element 365 such that the received input image light 355 isdecoupled out of output waveguide 320 via decoupling element 365.Directing element 360 is part of, or affixed to, first side 370-1 ofoutput waveguide 320. Decoupling element 365 is part of, or affixed to,second side 370-2 of output waveguide 320, such that directing element360 is opposed to the decoupling element 365. Directing element 360and/or decoupling element 365 may be, e.g., a diffraction grating, aholographic grating, one or more cascaded reflectors, one or moreprismatic surface elements, and/or an array of holographic reflectors.

Second side 370-2 represents a plane along an x-dimension and ay-dimension. Output waveguide 320 may be composed of one or morematerials that facilitate total internal reflection of image light 355.Output waveguide 320 may be composed of e.g., silicon, plastic, glass,and/or polymers. Output waveguide 320 has a relatively small formfactor. For example, output waveguide 320 may be approximately 50 mmwide along x-dimension, 30 mm long along y-dimension and 0.5-1 mm thickalong a z-dimension.

Controller 330 controls scanning operations of source assembly 310. Thecontroller 330 determines scanning instructions for the source assembly310. In some embodiments, the output waveguide 320 outputs expandedimage light 340 to the user's eyeball 220 with a large field of view(FOV). For example, the expanded image light 340 is provided to theuser's eyeball 220 with a diagonal FOV (in x and y) of 60 degrees and/orgreater and/or 150 degrees and/or less. The output waveguide 320 isconfigured to provide an eyebox with a length of 20 mm or greater and/orequal to or less than 50 mm; and/or a width of 10 mm or greater and/orequal to or less than 50 mm.

Moreover, controller 330 also controls image light 355 generated bysource assembly 310, based on image data provided by image sensor 370.Image sensor 370 may be located on first side 370-1 and may include, forexample, image sensors 120 a-120 d of FIG. 1A to generate image data ofa physical environment in front of the user (e.g., for locationdetermination). Image sensor 370 may also be located on second side370-2 and may include image sensors 150 a and 150 b of FIG. 1B togenerate image data of eyeball 220 (e.g., for gaze point determination)of the user. Image sensor 370 may interface with a remote console thatis not located within waveguide display 300. Image sensor 370 mayprovide image data to the remote console, which may determine, forexample, a location of the user, a gaze point of the user, etc., anddetermine the content of the images to be displayed to the user. Theremote console can transmit instructions to controller 330 related tothe determined content. Based on the instructions, controller 330 cancontrol the generation and outputting of image light 355 by sourceassembly 310.

FIG. 4 illustrates an embodiment of a cross section 400 of the waveguidedisplay 300. The cross section 400 includes source assembly 310, outputwaveguide 320, and image sensor 370. In the example of FIG. 4, imagesensor 370 may include a set of pixel cells 402 located on first side370-1 to generate an image of the physical environment in front of theuser. In some embodiments, there can be a mechanical shutter 404interposed between the set of pixel cells 402 and the physicalenvironment to control the exposure of the set of pixel cells 402. Insome embodiments, the mechanical shutter 404 can be replaced by anelectronic shutter gate, as to be discussed below. Each of pixel cells402 may correspond to one pixel of the image. Although not shown in FIG.4, it is understood that each of pixel cells 402 may also be overlaidwith a filter to control the frequency range of the light to be sensedby the pixel cells.

After receiving instructions from the remote console, mechanical shutter404 can open and expose the set of pixel cells 402 in an exposureperiod. During the exposure period, image sensor 370 can obtain samplesof lights incident on the set of pixel cells 402, and generate imagedata based on an intensity distribution of the incident light samplesdetected by the set of pixel cells 402. Image sensor 370 can thenprovide the image data to the remote console, which determines thedisplay content, and provide the display content information tocontroller 330. Controller 330 can then determine image light 355 basedon the display content information.

Source assembly 310 generates image light 355 in accordance withinstructions from the controller 330. Source assembly 310 includes asource 410 and an optics system 415. Source 410 is a light source thatgenerates coherent or partially coherent light. Source 410 may be, e.g.,a laser diode, a vertical cavity surface emitting laser, and/or a lightemitting diode.

Optics system 415 includes one or more optical components that conditionthe light from source 410. Conditioning light from source 410 mayinclude, e.g., expanding, collimating, and/or adjusting orientation inaccordance with instructions from controller 330. The one or moreoptical components may include one or more lenses, liquid lenses,mirrors, apertures, and/or gratings. In some embodiments, optics system415 includes a liquid lens with a plurality of electrodes that allowsscanning of a beam of light with a threshold value of scanning angle toshift the beam of light to a region outside the liquid lens. Lightemitted from the optics system 415 (and also source assembly 310) isreferred to as image light 355.

Output waveguide 320 receives image light 355. Coupling element 350couples image light 355 from source assembly 310 into output waveguide320. In embodiments where coupling element 350 is diffraction grating, apitch of the diffraction grating is chosen such that total internalreflection occurs in output waveguide 320, and image light 355propagates internally in output waveguide 320 (e.g., by total internalreflection), toward decoupling element 365.

Directing element 360 redirects image light 355 toward decouplingelement 365 for decoupling from output waveguide 320. In embodimentswhere directing element 360 is a diffraction grating, the pitch of thediffraction grating is chosen to cause incident image light 355 to exitoutput waveguide 320 at angle(s) of inclination relative to a surface ofdecoupling element 365.

In some embodiments, directing element 360 and/or decoupling element 365are structurally similar. Expanded image light 340 exiting outputwaveguide 320 is expanded along one or more dimensions (e.g., may beelongated along x-dimension). In some embodiments, waveguide display 300includes a plurality of source assemblies 310 and a plurality of outputwaveguides 320. Each of source assemblies 310 emits a monochromaticimage light of a specific band of wavelength corresponding to a primarycolor (e.g., red, green, or blue). Each of output waveguides 320 may bestacked together with a distance of separation to output an expandedimage light 340 that is multi-colored.

FIG. 5 is a block diagram of an embodiment of a system 500 including thenear-eye display 100. The system 500 comprises near-eye display 100, animaging device 535, an input/output interface 540, and image sensors 120a-120 d and 150 a-150 b that are each coupled to control circuitries510. System 500 can be configured as a head-mounted device, a wearabledevice, etc.

Near-eye display 100 is a display that presents media to a user.Examples of media presented by the near-eye display 100 include one ormore images, video, and/or audio. In some embodiments, audio ispresented via an external device (e.g., speakers and/or headphones) thatreceives audio information from near-eye display 100 and/or controlcircuitries 510 and presents audio data based on the audio informationto a user. In some embodiments, near-eye display 100 may also act as anAR eyewear glass. In some embodiments, near-eye display 100 augmentsviews of a physical, real-world environment, with computer-generatedelements (e.g., images, video, sound, etc.).

Near-eye display 100 includes waveguide display assembly 210, one ormore position sensors 525, and/or an inertial measurement unit (IMU)530. Waveguide display assembly 210 includes source assembly 310, outputwaveguide 320, and controller 330.

IMU 530 is an electronic device that generates fast calibration dataindicating an estimated position of near-eye display 100 relative to aninitial position of near-eye display 100 based on measurement signalsreceived from one or more of position sensors 525.

Imaging device 535 may generate image data for various applications. Forexample, imaging device 535 may generate image data to provide slowcalibration data in accordance with calibration parameters received fromcontrol circuitries 510. Imaging device 535 may include, for example,image sensors 120 a-120 d of FIG. 1A for generating image data of aphysical environment in which the user is located, for performinglocation tracking of the user. Imaging device 535 may further include,for example, image sensors 150 a-150 b of FIG. 1B for generating imagedata for determining a gaze point of the user, to identify an object ofinterest of the user.

The input/output interface 540 is a device that allows a user to sendaction requests to the control circuitries 510. An action request is arequest to perform a particular action. For example, an action requestmay be to start or end an application or to perform a particular actionwithin the application.

Control circuitries 510 provide media to near-eye display 100 forpresentation to the user in accordance with information received fromone or more of: imaging device 535, near-eye display 100, andinput/output interface 540. In some examples, control circuitries 510can be housed within system 500 configured as a head-mounted device. Insome examples, control circuitries 510 can be a standalone consoledevice communicatively coupled with other components of system 500. Inthe example shown in FIG. 5, control circuitries 510 include anapplication store 545, a tracking module 550, and an engine 555.

The application store 545 stores one or more applications for executionby the control circuitries 510. An application is a group ofinstructions, that, when executed by a processor, generates content forpresentation to the user. Examples of applications include: gamingapplications, conferencing applications, video playback applications, orother suitable applications.

Tracking module 550 calibrates system 500 using one or more calibrationparameters and may adjust one or more calibration parameters to reduceerror in determination of the position of the near-eye display 100.

Tracking module 550 tracks movements of near-eye display 100 using slowcalibration information from the imaging device 535. Tracking module 550also determines positions of a reference point of near-eye display 100using position information from the fast calibration information.

Engine 555 executes applications within system 500 and receives positioninformation, acceleration information, velocity information, and/orpredicted future positions of near-eye display 100 from tracking module550. In some embodiments, information received by engine 555 may be usedfor producing a signal (e.g., display instructions) to waveguide displayassembly 210 that determines a type of content presented to the user.For example, to provide an interactive experience, engine 555 maydetermine the content to be presented to the user based on a location ofthe user (e.g., provided by tracking module 550), or a gaze point of theuser (e.g., based on image data provided by imaging device 535), adistance between an object and user (e.g., based on image data providedby imaging device 535).

FIG. 6A, FIG. 6B, and FIG. 6C illustrates examples of an image sensorand its operations. As shown in FIG. 6A, image sensor 600 can include anarray of pixel cells, including pixel cell 601, and can generate digitalintensity data corresponding to pixels of an image. Pixel cell 601 maybe part of pixel cells 402 of FIG. 4. As shown in FIG. 6A, pixel cell601 may include a photodiode 602, a transfer gate 604, and a chargesensing device 606. Photodiode 602 may include, for example, a P-Ndiode, a P-I-N diode, a pinned diode, etc. Photodiode 602 can generatecharge upon receiving light within an exposure period, and the quantityof charge generated within the exposure period can be proportional tothe intensity of the light. Photodiode 602 can also store the generatedcharge. Transfer gate 604 may include, for example, ametal-oxide-semiconductor field-effect transistor (MOSFET), a bipolarjunction transistor (BJT), etc. Charge sensing device 606 may include,for example, a floating drain (FD) node of the transistor of transfergate 604, a pinned storage device formed from a pinned diode, etc.Towards the end of the exposure period, the transfer gate 604 can beenabled to transfer the charge stored in photodiode 602 to chargesensing device 606 to develop a voltage. An array of voltages, includingv₀₀, v₀₁, . . . v_(ji), can be obtained. The array of voltages can bequantized by an A/D converter (which can be external or internal to thepixel cells) into digital values. The digital values can be furtherprocessed to generate an image 610.

In FIG. 6A, the presence of charge sensing device 606 in each pixel cellenables image sensor 600 to perform a global shutter operation, even ifthe pixel cells have to share the A/D converter. Specifically,photodiode 602 of each pixel cell can be exposed to incident lightwithin the same global exposure period to generate charge. The chargecan be temporarily stored at charge sensing device 606 of the pixel cellat least until that pixel cell can access the A/D converter to quantizethe charge. With such arrangements, a global shutter operation can besupported even if the voltages generated by the pixel cells are notquantized simultaneously.

FIG. 6B and FIG. 6C illustrate cross-sectional views of examples ofimage sensor 600. Image sensor 600 can include a plurality of pixelcells 601 (e.g., pixel cells 601 a, 601 b, 601 c, etc.), with each pixelcell including photodiode 602 (e.g., photodiodes 602 a, 602 b, 602 c,etc.) and charge sensing devices 606 (e.g., charge sensing devices 606a, 606 b, 606 c, etc.). Charge sensing devices 606 can be, for example,pinned storage nodes, floating drain nodes, etc. As shown in FIG. 6B andFIG. 6C, image sensor 600 can be included in a semiconductor die 620having a front side surface 622 and a back side surface 624. Front sidesurface 622 can be the front side of a semiconductor wafer from whichsemiconductor die 620 is fabricated, whereas back side surface 624 canbe the back side of the semiconductor wafer. The front side of thesemiconductor wafer can receive doping, ion implantation, etc., to formphotodiode 602 and charge sensing devices 606, such that bothphotodiodes 602 and charge sensing devices 606 are closer to front sidesurface 622 than back side surface 624. Metal interconnects 626 (e.g.,metal interconnects 626 a, 626 b, 626 c, etc.) can be formed on frontside surface 622, as shown in FIG. 6B, or on back side surface 624, asshown in FIG. 6C. Metal interconnects 626 can be used to transfer chargefrom photodiodes 602 to charge sensing devices 606.

Image sensor 600 can have different configurations. For example, asshown in FIG. 6B, image sensor 600 can have a back side illumination(BSI) configuration, in which back-side surface 624 can be a lightreceiving surface for image sensor 600. Moreover, as shown in FIG. 6C,image sensor 600 can have a front side illumination (FSI) configuration,in which front-side surface 622 can be a light receiving surface forimage sensor 600. In both FIG. 6B and FIG. 6C, image sensor 600 mayinclude color filters 632 (e.g., filters 632 a, 632 b, 632 c, etc.) andmicrolens 634 (e.g., microlens 634 a, 634 b, 634 c, etc.) formed on thelight receiving surface. Light can go through microlens 634, colorfilters 632, and the light receiving surface (back side surface 624 inFIG. 6B, front side surface 622 in FIG. 6C) to reach photodiodes 602.

As described above, noise charge can be added to charge sensing devices606, which can introduce error to the light intensity measurementoperation. For example, in a case where charge sensing devices 606 arefloating drain nodes, dark currents due to crystallographic defects mayadd noise charge to the charge transferred from photodiodes 602. As thelight intensity measurement operation is based on measuring a quantityof charge generated by photodiodes 602 within the global shutter period,while the measurement is based on the charge stored in charge sensingdevices 606, the noise charge from dark currents can introduce error tothe light intensity measurement operation.

In a case where charge sensing devices 606 are pinned storage nodes ofpinned diodes, the dark currents may be reduced compared with floatingdrain nodes, but the pinned diodes can receive photons 640 via the lightreceiving surface and generate photon noise charge responsive to photons640, which can also be added to the charge transferred from photodiodes602. Floating drain nodes, although being susceptible to dark currents,typically generate less photon noise charge than pinned diodes. Chargesensing devices 606 in the FSI configuration of FIG. 6C can generatemore noise charge than in the BSI configuration of FIG. 6B becausecharge sensing devices 606 are closer to the light receiving surface inthe FSI configuration, and there is a lack of light-shielding structureto block photons 640 from reaching charge sensing devices 606. As aresult, in the FSI configuration, charge sensing devices 606 can receivemore photons 640 and generate more noise charge compared with the BSIconfiguration. Moreover, as shown in FIG. 6B and FIG. 6C, in a BSIconfiguration photodiodes 602 are positioned further away from the lightreceiving surface than in a FSI configuration. As a result, in a BSIconfiguration incident light needs to travel through a longer distancewithin semiconductor 620, and therefore subject to larger power loss,before reaching photodiodes 602 than in a FSI configuration. As aresult, an image sensor 600 having a BSI configuration typicallyprovides a lower light-to-charge conversion rate than a FSIconfiguration, which may reduce the sensitivity of image sensor 600especially in a low light environment.

FIG. 7A and FIG. 7B illustrate an example of a pixel cell 700. FIG. 7Aillustrates a cross-sectional structural view of pixel cell 700, whereasFIG. 7B illustrates a schematic view of pixel cell 700. Pixel cell 700can perform a global shutter operation with improved noise performance.As shown in FIG. 7A, a pixel cell 700 may include a first semiconductordie 702, a second semiconductor die 704, and a sampling capacitor 706forming a stack along a vertical direction (e.g., along the z-axis).First semiconductor die 702 may include a photodiode 716 and a chargesensing device 718. Second semiconductor die 704 may include interfacecircuits 720. In the example of FIG. 7A, sampling capacitor 706 caninclude a metal capacitor formed from one or more metal layers 708sandwiched between first semiconductor die 702 and second semiconductordie 704. In some examples, sampling capacitor 706 can also be formed asa device capacitor (e.g., a floating drain node, a pinned storage node,etc.) in one of first semiconductor die 702 or second semiconductor die704. By stacking photodiode 716, sampling capacitor 706, and interfacecircuits 720 along a vertical direction, the horizontal footprint ofpixel cell 700 (along the x/y axes) can be reduced, which allows packinga large number of pixel cells in an image sensor to improve resolutionwhile minimizing the footprint of the image sensor. Moreover, by formingthe sampling capacitor and the AC capacitor between the semiconductordies, these capacitors do not cover the light receiving surface, whichcan maximize the available pixel cell area for the light receivingsurface and allows the footprint of the pixel cell to be furtherreduced. With the disclosed techniques, a high resolution image sensorwith a small footprint can be achieved, which is especially useful forapplications on a wearable device (e.g., a headset) where availablespace is very limited.

As described above, first semiconductor die 702 may include photodiode716 and charge sensing device 718. Photodiode 716 can be exposed toincident light within an integration period to generate and storecharge. Towards the end of the integration period, the charge stored inphotodiode 716 can be transferred to charge sensing device 718 todevelop a voltage. Interface circuits 720 of second semiconductor die704 may include a control circuit 722 to control sampling capacitor 706to perform a sample-and-hold operation to sample the voltage and thenstore the voltage. Interface circuits 720 also include a processingcircuit 724 to perform a quantization operation on the stored voltage togenerate a digital output representing the intensity of the incidentlight received by photodiode 716. As to be described below, thesample-and-hold operation can reduce the exposure of sampling capacitor706 to dark currents, which can improve the accuracy of the lightsensing operation.

First semiconductor die 702 includes a front side surface 710 and a backside surface 712. Photodiode 716 and charge sensing device 718 can beformed by, for example, a doping process, an ion implantation process,etc., performed on front side surface 710, such that both photodiode 716and charge sensing device 718 are closer to front side surface 710 thanback side surface 712. To improve light-charge conversion rate, pixelcell 700 can have a FSI configuration in which front side surface 710 isconfigured as the light receiving surface, with a microlens 726 and acolor filter 728 positioned on front side surface 710 to focus andfilter the incident light. To reduce the effect of photon noise chargegeneration, charge sensing device 718 can be formed as a floating drainnode, a metal capacitor, a polysilicon capacitor, etc.

Referring to FIG. 7B, first semiconductor die 702 further includes othercircuits including, for example, an optional shutter switch 732, atransfer switch 734, a storage reset switch 736, a voltage buffer 738,and a sampling switch 740. The switches can be controlled by controlcircuit 722 to measure incident light intensity. Specifically, shutterswitch 732 (controlled by a signal labelled “AB”) can act as anelectronic shutter gate (in lieu of, or in combination with, mechanicalshutter 404 of FIG. 4) to control an exposure/integration period withinwhich photodiode 716 can accumulate charge for light intensitymeasurement. In some examples, shutter switch 732 can also be configuredas an anti-blooming gate to prevent charge generated by photodiode 716from leaking into other pixel cells when the photodiode saturates. Inaddition, transfer switch 734 can be controlled to transfer the chargefrom photodiode 716 to charge sensing device 718 to develop a voltage,which can be buffered by voltage buffer 738. Sampling switch 740,together with sampling capacitor 706, can be controlled to perform asample-and-hold operation of the buffered voltage. Storage reset switch736 can reset charge sensing device 718 prior to and after thesample-and-hold operation, to start over a new light intensitymeasurement.

FIG. 7C illustrates an example sequence of control signals for shutterswitch 732, transfer switch 734, storage reset switch 736, and samplingswitch 740 to perform a sample-and-hold operation. As shown in FIG. 7C,shutter switch 732 can be disabled (by de-asserting AB signal) at timeT0 to start an integration/shutter period within which photodiode 716can accumulate charge for light intensity measurement. Between times T0and T1, charge sensing device 718 can be in a reset state, with storagereset switch 736 enabled (by asserting the RST signal), while photodiode716 is accumulating charge. Between times T1 and T4 can be the samplingperiod, within which sampling switch 740 is enabled to electricallyconnect sampling capacitor 706 to the output of voltage buffer 738,which buffers the voltage of charge sensing device 718. During thesampling period, storage reset switch 736 can be disabled (byde-asserting the RST signal). The voltage across sampling capacitor 706can track the buffered voltage at charge sensing device 718. Betweentimes T2 and T3 within the sampling period, transfer switch 734 can beenabled to transfer the charge accumulated in photodiode 716 to chargesensing device 718. At time T3 transfer switch 734 can be disabled,which ends the integration period, and the voltage at charge sensingdevice 718 at time T3 can represent a quantity of charge accumulated byphotodiode 716 (and transferred to charge sensing device 718) within theintegration period between times T0 and T3. Sampling capacitor 706 cansample the buffered voltage at charge sensing device 718 until time T4,such that the voltage at sampling capacitor 706 tracks the bufferedvoltage at charge sensing device 718. After time T4, sampling capacitor706 can hold the sampled voltage, which can then be quantized byprocessing circuit 724 at a subsequent time after time T4.

An image sensor can include an array of pixel cells 700. To support aglobal shutter operation, the array of pixel cells 700 can share aglobal AB signal and a global TG signal so that a global integrationperiod starts at the same time T0 and ends at the same time T3 for eachpixel cell 700. The sampling capacitor 706 of each pixel cell can storethe voltage representing the charge accumulated by the photodiode 716 ofeach pixel cell within the global integration period. The voltagesstored in the pixels can then be quantized by one or more ADCs.

Compared with pixel cell 601 of FIG. 6, pixel cell 700 can provideimproved noise performance. Specifically, charge sensing device 718 isin a reset state for much of the integration period (e.g., from times T0and T1) and is out of the reset state during the sampling period. Chargesensing device 718 is more susceptible to dark currents and photons, andcan accumulate more dark currents noise charge and photon noise charge,during the sampling period compared with when charge sensing device 718is in the reset state. If the sampling period is relatively short, thenoise charge added to the charge transferred from photodiode 716 can bereduced. Moreover, by performing a sample-and-hold operation, samplingcapacitor 706 can be disconnected from charge sensing device 718 aftersampling the buffered voltage at charge sensing device 718, which canprevent dark currents from flowing into sampling capacitor 706 fromcharge sensing device 718 (or other components of first semiconductordie 702) which can contaminate the sampled voltage. Further, byimplementing sampling capacitor 706 as a metal capacitor rather than afloating drain node or a pinned storage node, sampling capacitor 706 canbe less susceptible to dark currents and photon noise charge whenholding the sampled voltage. All these can reduce the noise componentsin the voltage being quantized and can improve the accuracy of the lightsensing operations.

FIG. 7D illustrates an example of processing circuit 724. As shown inFIG. 7D, processing circuit 724 includes a comparator 750. Comparator750 can be coupled with a memory 760 which is also coupled with acounter 762. In some examples, memory 760 and counter 762 can be part ofpixel cell 700 and processing circuit 724. In some examples, as to bedescribed below, memory 760 and counter 762 can be external to pixelcell 700 and shared among an array of pixel cells 700, to reduce thefootprint of pixel cell 700.

Comparator 750, memory 760, and counter 762 can perform a quantizationprocess of the sampled voltage at sampling capacitor 706 (labelled“V_(S)”). Specifically, memory 760 can be a latch memory. Counter 762can update its output count value (labelled “cnt”) periodically based ona clock signal. Comparator 750 can compare an input voltage (labelled“V_(COMP_IN)”), which is derived from the sampled voltage at samplingcapacitor 706 (labelled “V_(S)”), with a ramping threshold voltage(labelled “VREF”) to generate a decision (labelled “V_(OUT)”). Thedecision can be a latch signal to control the latch memory to store acount value output by counter 762. When ramping VREF voltage reaches orexceeds V_(COMP_IN), the decision output of comparator 750 trips, andthe count value output by counter 762 when the decision trips can bestored in memory 760. The count value stored in memory 760 can representa quantization result of V_(COMP_IN) and of V_(S), which can represent ameasurement of the incident light intensity within the global shutterperiod of FIG. 7C.

As shown in FIG. 7D, pixel cell 700 further includes an AC capacitor 746and a comparator reset switch 752, which can be operated to compensatefor measurement errors (e.g., comparator offset) introduced bycomparator 750, as well as other error signals such as, for example,reset noise introduced to charge sensing device 718 (by assertion of theRST signal) which can be present in the V_(S) sampled voltage. ACcapacitor 746 can be implemented as a metal capacitor between firstsemiconductor die 702 and second semiconductor die 704. AC capacitor 746can be used to perform two sampling operations within the samplingperiod. A first sampling operation can be performed prior to transfer ofcharge from photodiode 716 to charge sensing device 718, which storesreset noise charge. As part of the first sampling operation, comparatorreset switch 752 can be enabled (by assertion of the COMP_RST signal)which can short the negative input and output terminals of thecomparator. As a result of the first sampling operation, AC capacitor746 can store a voltage (labelled “V_(CC)”) across the capacitor whichincludes a component of the reset noise and an offset voltage ofcomparator 750. A second sampling operation can then be performed, inwhich comparator reset switch 752 can be disabled, followed by enablingcharge transfer switch 742 to transfer the charge from photodiode 716 tocharge sensing device 718. The V_(COMP_IN) input voltage can include thelatest V_(S) sampled voltage (which represents the charge stored inphotodiode 716 and transferred to charge sensing device 718) and theV_(CC) voltage. The reset noise charge component in the latest V_(S)sampled voltage can be cancelled by the reset noise charge component ofthe V_(CC) voltage, while the comparator offset component in the V_(CC)voltage remains in the V_(COMP_IN) input voltage. The comparator offsetcomponent in the V_(COMP_IN) input voltage can cancel out orsubstantially reduce the effect of the comparator offset of comparator750 when comparator 750 compares the new V_(COMP_IN) input voltage withthe ramping threshold voltage. As both the comparator offset and resetnoise are eliminated or at least substantially reduced, the accuracy ofquantization can be improved.

FIG. 7D illustrates an example sequence of control signals for thesample-and-hold operation including COMP_RST. The timings of AB, RST,TG, and SAMPLE signals in FIG. 7C is identical to those in FIG. 7C andtheir descriptions are not repeated here. As shown in FIG. 7D, withinthe sampling period and between times T1 and T2, charge transfer fromphotodiode 716 to charge sensing device 718 has not started. The voltageat charge sensing device 718 (and the sampled voltage V_(S)) can be at areset voltage V_(S_rst) and can also include a reset noise componentVσ_(KTC). Between times T1 and T2, the sampled voltage V_(S) can be asfollows:

V _(S)(T2)=V _(S_rst) +Vσ _(KTC)  (Equation 1)

Moreover, with comparator reset switch 752 enabled, and the positiveterminal of comparator 750 connected to a VREF voltage, the voltage ofCOMP_IN (V_(COMP_IN)) can track the VREF voltage, but differ by thecomparator offset V_(comp_offset) as follows:

V _(COMP_IN)(T2)=V _(REF) +V _(comp_offset)  (Equation 2)

At time T2, the voltage difference V_(CC) between the right plate of ACcapacitor 746 (connected with COMP_IN) and the left plate of ACcapacitor 746 (connected with sampling capacitor 706) can be as follows:

V _(CC)(T2)=V _(COMP_IN)(T2)−V _(S)(T2)  (Equation 3)

Combining Equations 1, 2, and 3, the voltage difference V_(CC) at timeT2 can be as follows:

V _(CC)(T2)=(V _(REF) +V _(comp_offset))−(V _(S_rst) +Vσ_(KTC))  (Equation 4)

The voltage difference V_(CC)(T2) can represent a result of the firstsampling operation.

Between T2 and T3, charge transfer switch 734 is enabled, and charge istransferred from photodiode 716 to charge sensing device 718 to developa new voltage. At time T3, the sampled voltage V_(S)(T3) can include anew voltage V_(S_out) corresponding to the transferred charge can besampled by sampling capacitor 706, as well as the reset noise componentVσ_(KTC) which remains at charge sensing device 718, as follows:

V _(S)(T3)=V _(S_out) +Vσ _(KTC)  (Equation 5)

V_(S)(T3) can represent a result of the second sampling operation.

At time T3, the comparator reset switch 752 is disabled. The voltagedifference V_(CC) across AC capacitor 746 remains the same as at timeT2. Via AC-coupling, the voltage of the right plate of AC capacitor 746(V_(COMP_IN)) at time T3 can track V_(S)(T3) but differ by the voltagedifference V_(CC) as follows:

V _(COMP_IN)(T3)=V _(S)(T3)+V _(CC)(T2)  (Equation 6)

Combining Equation 6 with Equation 4 becomes:

V _(COMP_IN)(T3)=V _(S_out) +Vσ _(KTC)+(V _(REF) +V _(comp_offset))−(V_(S_rst) +Vσ _(KTC))  (Equation 7)

As shown in Equation 7, the Vσ_(KTC) component of V_(S)(T3) and theVσ_(KTC) component of V_(CC)(T2) (and V_(CC)(T3)) can be cancelled out.Equation 7 can be simplified as follows:

V _(COMP_IN)(T3)=V _(S_out) −V _(S_rst) +V _(REF) +V_(comp_offset)  (Equation 8)=

After T3, the voltage at V_(COMP_IN) can be held at V_(COMP_IN) (T3)when no additional charge is transferred to charge sensing device 718and/or after sampling switch 740 is disabled.

As shown in Equation 8, V_(COMP_IN) (T3) includes a difference componentV_(S_out)−V_(S_rst), which represents the quantity of charge from thephotodiode and transferred to charge sensing device 718 between times T2and T3. V_(COMP) _(IN) (T3) further includes the V_(comp_offset)component as well as V_(REF) (from V_(CC)). When comparator 470 comparesV_(COMP_IN) with V_(REF), the comparator offset introduced by comparator470 can be cancelled by the V_(comp_offset) component, and only thedifference V_(S_out)−V_(S_rst), which represents the quantity of chargefrom the photodiode, is compared against V_(REF) as part of thequantization process to generate the quantization result. Sucharrangements can remove the reset noise and comparator offset from thequantization result and improve the accuracy of light intensitymeasurement.

As described above, to further reduce the footprint of pixel cell 700,memory 760 and counter 762 can be positioned external to pixel cell 700and can be shared among a set of pixel cells 700. FIG. 8A illustrates anexample image sensor 800 which includes shared counter and memories. Asshown in FIG. 8A, image sensor 800 includes a first semiconductor die802 and a second semiconductor die 804. Semiconductor die 802 includesan array of light sensing circuits 806, including light sensing circuits806 a, with each light sensing circuit 806 including photodiode 716,charge sensing device 718, shutter switch 732, transfer switch 734,storage reset switch 736, voltage buffer 738, and sampling switch 740.Semiconductor die 804 includes an array of interface circuits 808,including interface circuits 808 a. Each interface circuit 808 includescomparator 750 and comparator reset switch 752 and corresponds to eachlight sensing circuit 806. Image sensor 800 further includes an array ofsampling capacitors 706 and an array of AC capacitors 746. Each samplingcapacitor 706 and AC capacitor 746 is coupled between a correspondingpair of light sensing circuit 806 and interface circuit 808 to form apixel cell 810. The arrays of sampling capacitors 706 and AC capacitors746 can be formed in a metal layer 812 stacked between firstsemiconductor die 802 and second semiconductor die 804. The lightsensing operations of light sensing circuits 806 and interface circuits808 using sampling capacitors 706 and AC capacitors 746 are similar tothe operations described in FIGS. 7B-7E and are not repeated here.

In addition, image sensor 800 includes a counter 820, a bank of memorybuffers 822, and a controller 824, some or all of which can be part ofinterface circuits 808. Each memory buffer 822 within the bank can be alatch memory similar to memory 760. Counter 820 can update a count value(“cnt”) periodically based on a clock. Counter 820 can output the countvalue to bank of memory buffers 822. Pixel cells 810 can control thetiming of when the count values are stored in bank of memory buffers 822based on comparing the sampled voltages stored at the pixel cellsagainst a ramping threshold to quantize the sampled voltages, asdescribed above. Controller 824 can control the access to bank of memorybuffers 822 among pixel cells 810 to quantize the sampled voltages. InFIG. 8A, controller 824 can allow one row of pixel cells 810 (e.g., aset of pixel cells aligned along the x-axis of FIG. 8A) to access bankof memory buffers 822 to quantize the sampled voltages at the row ofpixel cells 810, followed by another row. Within a column of pixel cells810 (e.g., a set of pixel cells aligned along the y-axis of FIG. 8A),comparator 750 of each pixel cell can be selectively coupled with amemory buffer within the bank via a row switch 830. Comparator 750 ofeach pixel cell is also selectively coupled with a power supply via apower switch 832.

FIG. 8B and FIG. 8C illustrate example sequences of control signals forimage sensor 800. The sequence of control signals for FIG. 8B can be,for an example, of pixel cell 810 that includes shutter switch 732,whereas the sequence of control signals for FIG. 8C can be, for anexample, of pixel cell 810 that does not include shutter switch 732. InFIG. 8B and FIG. 8C, the RST, TG, AB, and COMP_RST can be global signalsto each pixel cell to perform a global shutter operation in a globalintegration period, as well as a first sampling operation (to samplereset noise charge and comparator offset) and a second samplingoperation (to sample charge accumulated in the global integrationperiod) in a sampling period. Following the sampling period, rows ofpixel cells 810 can take turn to access bank of memory buffers 822 toperform quantization. For example, when a first row of pixel cells 810is selected to access bank of memory buffers 822, row switch 830 of eachpixel cell within the row (labelled “ROW[1]”) is enabled to couple theoutput of comparator 750 to memory buffer 822, whereas power switch 832of each pixel cell within that row (labelled “ON[1]”) is enabled bycontroller 824 to enable comparator 750. Comparator 750 of each pixelcell can compare the sampled voltage stored at the pixel cell againstramping threshold V_(REF) to generate a decision, which can betransmitted via row switch 830 to control a time when memory buffer 822stores the count value from counter 820. The count values stored in bankof memory buffers 822 can represent the quantization results for firstrow of pixel cells 810. The count values in bank of memory buffers 822can be read out (e.g., by an image reconstruction engine) via data_outbuses. After the count values are read out from the bank of memorybuffers for the first row of pixel cells 810, row switches 830 and powerswitches 832 of the first row of pixel cells 810 (ROW[1] and ON[1]) canbe disabled by controller 824. Controller 824 can then select a secondrow of pixel cells 810 to access bank of memory buffers 822 to quantizethe sampled voltages stored at the second row of pixel cells 810. Rowswitch 830 and power switch 832 of the second row of pixel cells (ROW[2]and ON[2]) can be enabled by controller 824 to perform the quantization.

Although FIG. 8A illustrates that a single bank of memory buffers 822 isshared among rows of pixel cells 810, it is understood that multiplebanks of memory buffers can be provided, which can increase the numberof pixel cells that can concurrently perform quantization with counter820 and with the memory buffers, and the speeds of read out and imagegeneration can be increased. For example, as shown in FIG. 8D, twomemory banks 850 and 852 can be provided. First memory bank 840 can beshared among rows 850 of pixel cells 810, whereas bottom memory bank 842can be shared among rows 852 of pixel cells 810. Moreover, as shown inFIG. 8E, four memory banks 860, 862, 864, and 866 can be provided.Memory bank 870 can be shared among rows 880 a and 880 b of pixel cells810, memory bank 872 can be shared among rows 882 a and 882 b of pixelcells 810, memory bank 874 can be shared among rows 884 a and 884 b ofpixel cells 810, whereas memory bank 876 can be shared among rows 886 aand 886 b of pixel cells 810.

The arrangements in FIG. 8A-FIG. 8E, by putting the memory external tothe pixel cell, can further the footprint of the pixel cells, whichallows packing a large number of pixel cells in an image sensor toimprove resolution while minimizing the footprint of the image sensor.Moreover, the reliability and speed of image generation can also beimproved. For example, as the memory is positioned outside the pixelcell and does not affect the footprint of the pixel cell, redundantmemory devices can be provided to store the digital outputs from eachpixel cell to reduce the likelihood of losing the digital outputs (andthe pixel values) due to defective memory. But since the memorycomprises mostly digital circuit and typically has a very smallfootprint, adding redundant memory (to be shared by the pixel cells)typically do not significantly increase the footprint of the imagesensor. Moreover, compared with an implementation where the pixel celltransmits an analog voltage (e.g., a voltage at the charge sensingdevice) to an external ADC to perform the quantization operation, thedisclosed techniques allow a part of the quantization (the comparatorcomparison) operation to be performed within the pixel cell, and only adigital output (the decision of the comparator) is transmitted from thepixel cell to the external memory. Compared with an analog voltage, thedigital output can be transmitted with high fidelity (to distinguishbetween zeroes and ones) and at high speed. All these can improve thereliability and speed of image generation based on the light sensingoperations by the pixel cells.

FIG. 9 includes a flowchart that illustrates an example method 900 forperforming measurement of light intensity. Method 900 can be performedby, for example, pixel cell 700 of FIG. 7A-FIG. 7E and image sensor 800of FIG. 8A-FIG. 8D based on the techniques described above.

In step 902, an interface circuit (e.g., interface circuits 720,interface circuit 808) can enable a photodiode of a light sensingcircuit (e.g., light sensing circuit 806) to accumulate chargeresponsive to incident light within a integration period. The lightsensing circuit can be in a first semiconductor die (e.g., firstsemiconductor dies 702, 802, etc.), whereas the interface circuit can bein a second semiconductor die (e.g., second semiconductor dies 704, 804,etc.). The first semiconductor die and the second semiconductor die mayform a stack, as shown in FIG. 7A and FIG. 8A. The light sensing circuitin the first semiconductor die can be configured as a front-sideillumination device or a back-side illumination device as shown in FIG.6A and FIG. 6B. The enabling can be based on, for example, disablingshutter switch 732 to enable the photodiode to accumulate charge.

In step 904, the interface circuit can transfer the charge from thephotodiode to a charge sensing device (e.g., charge sensing device 718)of the light sensing circuit. The transfer can be performed via transferswitch 734 under the control of the interface circuit. The chargesensing device can be, for example, a floating drain device, a metalcapacitor, a polysilicon capacitor, etc.

In step 906, the interface circuit can perform, using a samplingcapacitor (e.g., sampling capacitor 706), a sample-and-hold operation toconvert the charge stored in the charge sensing device into a voltage.Specifically, the sampling capacitor can be coupled with the chargesensing device via a sampling switch controlled by the interfacecircuit. Referring back to FIG. 7C, within a sampling period, thetransfer switch can be enabled, as part of step 904, to transfer thecharge from the photodiode to the charge sensing device to develop avoltage, while the sampling switch is also enabled to enable thesampling capacitor to track the voltage of the charge sensing device.The transfer switch can be disabled prior to the end of the samplingperiod to freeze the voltage at the charge sensing device, and thesampling capacitor to continue tracking the voltage at the chargesensing device until the sampling period ends. After the sampling periodends, the sampling switch can be disabled, and the sampling capacitorcan hold the sampled voltage for a subsequent quantization process.

In some examples, the interface circuit can include a resetablecomparator (e.g., comparator 750) and an AC capacitor (e.g., ACcapacitor 746). Referring back to FIG. 7E, as part of step 906, thecomparator can be reset within the sampling period to store comparatoroffset and reset noise (which is also present in the charge sensingdevice and reflected in the sampled voltage at the sampling capacitor)in the AC capacitor. The AC capacitor can also track the voltage sampledand held by the sampling capacitor and combine the sampled voltage withthe reset noise and comparator offset information to generate an outputvoltage (e.g., V_(COMP_IN)).

In step 908, the interface circuit can generate a digital output basedon the voltage sample and held at the sampling capacitor to represent anintensity of the incident light received by the photodiode. The digitaloutput can be generated based on a quantization process, in which thecomparator can compare the output voltage of the AC capacitor with aramping threshold to generate a decision. The decision can control amemory (e.g., memory 760, 822, etc.) to store a digital value generatedfrom a counter (e.g., counter 762, 820, etc.). The memory and thecounter can be shared by multiple pixel cells, as described in FIG. 8Ato FIG. 8E, such that groups of pixel cells can take turn in storing thedigital values at the shared memory.

Some portions of this description describe the embodiments of thedisclosure in terms of algorithms and symbolic representations ofoperations on information. These algorithmic descriptions andrepresentations are commonly used by those skilled in the dataprocessing arts to convey the substance of their work effectively toothers skilled in the art. These operations, while describedfunctionally, computationally, or logically, are understood to beimplemented by computer programs or equivalent electrical circuits,microcode, or the like. Furthermore, it has also proven convenient attimes, to refer to these arrangements of operations as modules, withoutloss of generality. The described operations and their associatedmodules may be embodied in software, firmware, and/or hardware.

Steps, operations, or processes described may be performed orimplemented with one or more hardware or software modules, alone or incombination with other devices. In some embodiments, a software moduleis implemented with a computer program product comprising acomputer-readable medium containing computer program code, which can beexecuted by a computer processor for performing any or all of the steps,operations, or processes described.

Embodiments of the disclosure may also relate to an apparatus forperforming the operations described. The apparatus may be speciallyconstructed for the required purposes, and/or it may comprise ageneral-purpose computing device selectively activated or reconfiguredby a computer program stored in the computer. Such a computer programmay be stored in a non-transitory, tangible computer readable storagemedium, or any type of media suitable for storing electronicinstructions, which may be coupled to a computer system bus.Furthermore, any computing systems referred to in the specification mayinclude a single processor or may be architectures employing multipleprocessor designs for increased computing capability.

Embodiments of the disclosure may also relate to a product that isproduced by a computing process described herein. Such a product maycomprise information resulting from a computing process, where theinformation is stored on a non-transitory, tangible computer readablestorage medium and may include any embodiment of a computer programproduct or other data combination described herein.

The language used in the specification has been principally selected forreadability and instructional purposes, and it may not have beenselected to delineate or circumscribe the inventive subject matter. Itis therefore intended that the scope of the disclosure be limited not bythis detailed description, but rather by any claims that issue on anapplication based hereon. Accordingly, the disclosure of the embodimentsis intended to be illustrative, but not limiting, of the scope of thedisclosure, which is set forth in the following claims.

What is claimed is:
 1. A method comprising: within an integrationperiod: enabling a photodiode of a pixel cell to accumulate chargeresponsive to incident light, and transferring the charge from thephotodiode to a charge storage device of the pixel cell; performing,using a sampling capacitor, a sample-and-hold operation to convert thecharge stored in the charge storage device into a voltage; andgenerating a digital output based on the voltage to represent anintensity of the incident light received by the photodiode.
 2. Themethod of claim 1, wherein the sampling-and-hold operation comprises:enabling a sampling switch to cause the sampling capacitor to sample thecharge stored in the charge storage device to develop the voltage; anddisabling the sampling switch to cause the sampling capacitor to holdthe voltage.
 3. The method of claim 2, wherein the enabling of thesampling switch starts at a first time within the integration period andends at a second time after the integration period ends.
 4. The methodof claim 3, wherein the transferring of the charge from the photodiodeto the charge storage device starts after the first time and ends beforethe second time.
 5. The method of claim 1, wherein: the pixel cellfurther includes a shutter switch coupled with the photodiode; theintegration period is started based on disabling the shutter switch; andthe integration period is ended based on enabling the shutter switch. 6.The method of claim 1, wherein the pixel cell further includes: atransfer switch coupled between the photodiode and the charge storagedevice; and a reset switch coupled with the charge storage device;wherein the integration period is started based on disabling the resetswitch and the transfer switch; and wherein the integration period isended based on enabling the reset switch and the transfer switch.
 7. Themethod of claim 6, wherein generating the digital output based on thevoltage comprises: generating, using a comparator, a decision based onthe voltage and a threshold; controlling a memory to store a count valuefrom a counter based on the decision; and providing the count value asthe digital output.
 8. The method of claim 7, wherein the thresholdincreases or decreases with time; and wherein the count value measures atime when the threshold intersects with the voltage.
 9. The method ofclaim 7, further comprising: resetting the comparator prior totransferring the charge.
 10. The method of claim 9, wherein the chargestorage device is coupled with the comparator via an AC capacitor;wherein the voltage is a first voltage; wherein the method furthercomprises: obtaining, using the AC capacitor, a first sample of a resetvoltage of the charge storage device caused by a prior reset operationof the charge storage device; obtaining, using the AC capacitor, asecond sample of an offset of the comparator when the comparator is inthe reset state; storing a second voltage across the AC capacitor basedon the first sample of the reset voltage and the second sample of theoffset; and outputting, based on the first voltage and the secondvoltage, a third voltage to the comparator; and wherein the digitaloutput is generated based on the third voltage.
 11. The method of claim7, wherein an output of the comparator is coupled with the memory via aselection switch; and wherein the method further comprises: enabling theselection switch to transmit the decision to the memory when the pixelcell is selected to store the digital output in the memory; anddisabling the selection switch to block the decision from the memorywhen the pixel cell is not selected to store the digital output in thememory.
 12. The method of claim 7, wherein the comparator is coupledwith a power supply via a power switch; and wherein the method furthercomprises: enabling the power switch to enable the comparator togenerate the decision when the pixel cell is selected to store thedigital output in the memory; and disabling the power switch to disablethe comparator when the pixel cell is not selected to store the digitaloutput in the memory.
 13. The method of claim 7, wherein the comparatoris part of the pixel cell.
 14. The method of claim 1, wherein the chargestorage device comprises at least one of: a floating drain node, or apinned storage node.
 15. A method comprising: within an integrationperiod: enabling a first photodiode to accumulate a first chargeresponsive to incident light; transferring the first charge from thefirst photodiode to a first charge storage device; enabling a secondphotodiode to accumulate a second charge responsive to the incidentlight; and transferring the second charge from the second photodiode toa second charge storage device; performing, using a first samplingcapacitor, a first sample-and-hold operation to convert the first chargestored in the first charge storage device into a first voltage;performing, using a second sampling capacitor, a second sample-and-holdoperation to convert the second charge stored in the second chargestorage device into a second voltage; generating a first digital outputbased on the first voltage to represent an intensity of the incidentlight received by the first photodiode; storing the first digital outputat a memory; reading the first digital output from the memory;generating a second digital output based on the second voltage torepresent an intensity of the incident light received by the secondphotodiode; and after the first digital output is read from the memory,storing the second digital output at the memory.
 16. The method of claim15, further comprising: within the integration period: enabling a thirdphotodiode to accumulate a third charge responsive to incident light;and transferring the third charge from the third photodiode to a thirdcharge storage device; performing, using a third sampling capacitor, athird sample-and-hold operation to convert the third charge stored inthe third charge storage device into a third voltage; generating a thirddigital output based on the third voltage to represent an intensity ofthe incident light received by the third photodiode; and storing thefirst digital output and the third digital output at the memory prior toreading of the first digital output from the memory.
 17. The method ofclaim 16, wherein the first photodiode is part of a first pixel cell;wherein the second photodiode is part of a second pixel cell; andwherein the third photodiode is part of a third pixel cell.
 18. Themethod of claim 16, wherein the first pixel cell and the third pixelcell are in a first row of pixel cells of an image sensor; and whereinthe second pixel cell is in a second row of the pixel cells of the imagesensor.
 19. The method of claim 16, wherein each of the first, second,and third digital outputs is generated using, respectively, a firstcomparator, a second comparator, and a third comparator; and wherein thefirst, second, and third comparators are reset during, respectively, thefirst, second, and third sample-and-hold operations.
 20. The method ofclaim 19, wherein: the first comparator is part of the first pixel cell;the second comparator is part of the second pixel cell; and the thirdcomparator is part of the third pixel cell.